1. Field of the Invention
The present general inventive concept relates to a DC/DC converter, and more particularly, to a buck direct current/direct current (DC/DC) voltage converter (hereinafter, referred to as a ‘converter’) to perform an improved switching operation by adjusting a variable resistor according to an output current of the converter.
2. Description of the Related Art
In general, most electronic devices use a DC voltage (to power an IC semiconductor) or multiple DC voltage levels produced by an adaptor using a DC/DC converter to divide a DC voltage of a predetermined level, for example, 5 V, 3.3 V or 8 V from 12 V.
FIG. 1 is a schematic block diagram illustrating a conventional DC/DC converter 100. The DC/DC converter 100 includes a switching circuit 110, a switching controller 120, a bootstrap circuit 130, and a smoothing circuit 140.
The switching circuit 110 receives an input power and outputs a square wave having a predetermined duty ratio by a switching operation.
The switching controller 120 controls the switching operation of the switching circuit 110. In addition, the bootstrap circuit 130 is associated with the switching circuit 110 and the switching controller 120 and provides power to a circuit for driving the switching circuit 110. The smoothing circuit 140 converts the square wave output from the switching circuit 110 into a DC voltage having a predetermined value as an output power.
FIG. 2 is a detailed circuit diagram illustrating the conventional DC/Dc converter 100 of FIG. 1.
Referring to FIGS. 1 and 2, the switching circuit 110 includes a pair of FETs Q1 and Q2. Each input of the FETs Q1 and Q2 has a pulse-width modulation (PWM) signal inverted with dead time. The square wave having a predetermined duty ratio is output from an output node 112 by the switching operation. A control integral circuit (IC) is used as the switching controller 120 for controlling the switching operation of the switching circuit 110 in response to a voltage Vdc and the each input. The switching controller 120 includes a terminal HO for providing an input signal to the FET Q1, a terminal LO for providing an input signal to the FET Q2, a terminal Vcc for driving the switching controller 120, and terminals Vb and Vs for providing power used to drive the FET Q1 in the switching controller 120. In this case, a square waveform output from the terminals HO and LO is a PWM signal waveform inverted with dead time.
The bootstrap circuit 130 includes a bootstrap diode and a capacitor C1. When the output node 112 of the switching circuit 110 is grounded, that is, when the FET Q1 is turned off and the FET Q2 is turned on, charges accumulate in the capacitor C1 via the bootstrap diode from a 5V source. As such, a voltage Vbs is formed between the terminals Vb and Vs. The voltage Vbs is used to drive the FET Q1. In general, the smoothing circuit 140 includes passive devices such as a resistor, an inductor, and a capacitor. In FIG. 2, an inductor and a capacitor are used in the smoothing circuit 140. The smoothing circuit 140 converts the square wave output from the output node 112 of the switching circuit 110 into a DC waveform to provide a predetermined DC voltage Vout.
A resistor R 122 is connected between the bootstrap circuit 130 and the switching controller 120sto control the FET Q1 of the switching circuit 110 so as to quickly perform the switching operation, which results in a high peak voltage at the output node 112 when a state of the FET Q1 is changed from an off state to an on state, and the high peak voltage may exceed a radiated EMI margin. FIG. 3 is a diagram illustrating output waveforms A and B of the switching circuit 110 of FIGS. 1 and 2 with and without a resistor R122, respectively. The waveform A is generated at the output node 112 when the resistor 122 is not used.
When the resistor R 122 is inserted between the bootstrap circuit 130 and the control IC 120. When a gate input impedance of the FET Q1 varies, a peak ringing voltage of the output node 112 can be reduced as shown in FIG. 2. The waveform B is generated at the output node 112 when the resistor R 122 is used as shown in FIG. 3. However, in this case, a switching operation time in the switching circuit 110 increases, so that a switching loss is generated.
That is, since the resistor R 122 is set to reduce the peak voltage generated at the output node 112 by a maximum load current of the converter, even when a small load current is generated in the converter, an unnecessary switching loss is generated by an increased switching time.
Thus, the peak voltage generated at the output node 112 of the switching circuit 110 is reduced, and simultaneously, the switching time of the FET Q1 can be adjusted by a load current of the converter. Thus, a method to reduce the switching loss is needed.